The fabrication of integrated circuits includes many diverse processing steps. One of the operations frequently employed is the deposition of a dielectric film into a gap between features patterned over or into semiconductor wafers. One of the goals in depositing such material is to form a void-free, seam-free fill in the gap.
While deposition methods such as high density plasma (HDP), sub-atmospheric chemical vapor deposition (SACVD), and low pressure chemical vapor deposition (LPCVD) have been used for gap fill, these methods do not achieve the desired fill capability and conformality. Flowable chemical vapor deposition and spin-on dielectric (SOD) methods can achieve the desired fill, but tend to deposit highly porous films. Further, these methods are especially complex and costly to integrate, as they require many extra processing steps. Atomic layer deposition (ALD) processes have also been used for gap fill for improved conformality, but these processes suffer from long processing times and low throughput, especially for large gaps. Furthermore, the conformal nature of ALD processes means that the aspect ratios of the gaps increase with successive cycles. Hence, the top of a gap may fill more quickly than the bottom, preventing further diffusion of precursor materials into the gap. Areas can expand such that voids may form in the middle of high aspect ratio gaps.
In some cases, multi-step deposition processes are used, including deposition-etch-deposition processes which require distinct etching operations between subsequent deposition operations. The etching may be done to remedy or prevent void formation in the gap. Specifically, the etch step can be an anisotropic etch that creates a tapered positive slope profile so that gap fill can occur by depositing a subsequent layer on a positive tapered slope rather than a vertical slope. This can minimize the occurrence of void formation in the gap. Voids may lead to high resistance, contamination, loss of filled materials, and otherwise degrade performance of integrated circuits.